1. Technical Field
The present invention relates to a semiconductor laser and a method of manufacturing the same.
2. Related Art
Semiconductor lasers using an AlGaInAs quantum well in an active layer can perform laser oscillation with a low threshold current and high efficiency, or direct modulation at a high speed of more than 10 Gb/s even in a high-temperature environment, as compared to when InGaAsP is used. The reason is that, since the band offset of the conduction band of AlGaInAs quantum well is large, a strong electron confinement occurs, it is possible to prevent the overflow of electrons from an active layer at a high temperature, and a high differential gain is obtained. As a result, a semiconductor laser capable of performing direct modulation at a speed of 10 Gb/s without adjusting the temperature is manufactured.
There is an increasing demand for a 10 Gb/s small optical transceiver that can be mounted with high density and has a low power consumption, with an increase in transmission capacity. In particular, a high-speed small form-fact or pluggable (SFP+) optical transceiver has a power consumption of 1 W or less, and it is necessary to reduce the operation current of the semiconductor laser used in the optical transceiver.
An embedded structure capable of injecting a current into the active layer with high efficiency is used in order to reduce the operation current of the semiconductor laser. The semiconductor laser with an embedded structure using the InGaAsP quantum well in the active layer can be formed by forming a mesa structure using etching and forming a current block layer using buried growth. However, when the same process is applied to AlGaInAs quantum well, the side of the active layer is oxidized by etching for forming the mesa structure. As a result, it is difficult to manufacture a high-reliability semiconductor laser.
Therefore, T. Okuda, et al., “Low-Operation-Current and Highly-Reliable 1.3-μm AlGaInAs Strain Compensated MQW-BH-DFB Lasers for 100° C., 10-Gb/s Operation”, The Optical Fiber Communications Conference, 2004, Conference Digest, ThD3, pp. 65-67, or Japanese Unexamined Patent Publication No. 2003-133647 discloses a structure in which a semiconductor waveguide with a mesa shape including Al is formed by selective growth, and a p-type InP protective layer 10 is continuously grown so as to cover the entire waveguide, thereby completely preventing the oxidation of a semiconductor layer (strain-compensated multiple quantum well active layer 6) including Al, as shown in FIG. 18.
As a result, a high-reliability semiconductor laser with an embedded structure using an AlGaInAs quantum well in an active layer is achieved which is stably operated for 4,000 hours at a temperature of 85° C. and has a median life of 100,000 hours or more (FIG. 19). FIGS. 18 and 19 are disclosed in T. Okuda, et al.
However, the related art disclosed in the above-mentioned documents has the following problems.
When the growth time of the protective layer is shortened in order to reduce the thickness of the top of the mesa in terms of a reduction in leakage current, the thickness of the side of the mesa of the protective layer is reduced. As a result, the active layer including Al is likely to be exposed and oxidized.
As a result, it is difficult to manufacture a high-reliability semiconductor laser with high yield.
FIG. 20 is an enlarged cross-sectional view illustrating near the active layer waveguide of the semiconductor laser shown in FIG. 19. In T. Okuda, et al., an n-type InGaAsP guide layer 3, an n-type InP buffer layer 4, and a strain-compensated multiple quantum well active layer 6 made of AlGaInAs are formed on an n-type InP substrate 1. The waveguide with a mesa structure including the strain-compensated multiple quantum well active layer 6 is covered with a p-type InP protective layer 10. In the semiconductor laser shown in FIG. 20, an Fe-doped high-resistance InP layer 11 and an n-type InP layer 12 are used as the current block layers. The Fe-doped high-resistance InP layer 11 is used to reduce the parasitic capacitance of the device in order to achieve a high-speed operation. However, the Fe-doped high-resistance InP layer 11 traps electrons, but does not trap holes. Therefore, a portion of a hole current injected through the p-type InP clad layer 13 leaks through the p-type InP protective layer 10 and the high-resistance InP layer 11 (the leakage current is represented by an arrow in FIG. 20).
In order to reduce the leakage current, it is effective to reduce the distance dw between the n-type InP current block layer 12 and the active layer waveguide corresponding to the width of a leakage path (dw is shown in FIG. 20).
FIG. 21 is an enlarged cross-sectional view illustrating the active layer waveguide with a mesa shape shown in FIG. 18. The active layer waveguide including the strain-compensated multiple quantum well active layer 6 is formed in an opening of a pair of silicon oxide masks 17 by selective growth and is then covered with the p-type InP protective layer 10. The width dw of the leakage path is equal to the thickness dt of the top of the mesa of the p-type InP protective layer 10 shown in FIG. 21 (dt is shown in FIG. 21). Therefore, it is necessary to decrease the thickness dt in order to reduce the width dw of the leakage path.
However, when the growth time of the InP protective layer is shortened in order to reduce the thickness dt, the thickness ds of the side of the mesa of the p-type InP protective layer 10 is also reduced (ds is shown in FIG. 21). As a result, the strain-compensated multiple quantum well active layer 6 including Al is likely to be exposed and oxidized.
In Japanese Unexamined Patent Publication No. 2003-133647, in order to increase the ds/dt ratio, the (100) plane of the semiconductor substrate is inclined in the [011] direction or the [0-1-1] direction, or the growth conditions of the InP protective layer are optimized to increase the thickness ds of the side of the mesa. As a result, as described in the first to third embodiments of Japanese Unexamined Patent Publication No. 2003-133647, the thickness dt of the top of the mesa of the p-type InP protective layer is 200 nm, and the thickness ds of the side of the mesa is in the range of 20 nm to 30 nm. Therefore, a mesa shape having a ds/dt ratio of 0.1 to 0.15 is formed.
However, in Japanese Unexamined Patent Publication No. 2003-133647, since the thickness dt of the top of the mesa of the p-type InP protective layer corresponding to the width dw of the leakage path is 200 nm, it is necessary to decrease the thickness dt to reduce the leakage current. In addition, similar to T. Okuda, et al., when the growth time of the InP protective layer is shortened in order to reduce the thickness dt, the thickness ds is also reduced. As a result, the strain-compensated multiple quantum well active layer including Al is likely to be exposed and oxidized.